Director – ASIC Design, Alphawave Semi | Bengaluru, Karnataka, India
[LinkedIn Profile](https://in.linkedin.com/in/rathish-chandran-)
Professional Role and Expertise:
Rathish Chandran serves as the Director of ASIC Design at Alphawave Semi, a company specializing in semiconductor IP solutions. He is based in Bengaluru, India. Rathish brings 24 years of industry experience in the semiconductor domain, with a specialized focus on physical design and timing closure for ASIC (Application-Specific Integrated Circuit) development. His technical expertise encompasses the core implementation flows critical to semiconductor chip design, emphasizing performance optimization and design closure challenges.
Industry Experience and Contributions:
- Over two decades of continuous involvement in ASIC design projects, underscoring deep familiarity with complex semiconductor design cycles and methodologies.
- Proven leadership in physical design disciplines, managing high-impact ASIC design teams and workflows within Alphawave Semi, a technology IP leader.
- Engagement with Advanced ASIC design flows, including automation and optimization techniques such as layout reuse and timing-driven design, as reflected in presentations and professional participation in design automation forums.
Professional Activities and Industry Engagement:
- Rathish Chandran has been prominently involved as a session chair and contributor in notable semiconductor and design automation conferences, particularly the Design Automation Conference (DAC) and the 58th DAC event, where he contributed to the “Designer, IP and Embedded Systems Track.”
- His participation at such forums highlights a role in shaping discussions around performance modeling and digital processing system design, signaling Rathish’s active involvement in advancing ASIC design innovation through industry collaborations and knowledge exchange platforms.
- Previously affiliated with Intel Technology India Pvt. Ltd., indicating a strong background in global semiconductor firms before his current leadership at Alphawave Semi.
Technical Expertise and Domain Focus:
- Specializes in physical design, including layout generation and timing closure, both critical to successful tape-out cycles for ASIC products.
- Experience extends to the automated generation of design elements such as Current Controlled Oscillator (CCO) layouts using template reuse flows, showcasing familiarity with cutting-edge ASIC design automation techniques.
- Has contributed to or been involved in talks and technical presentations addressing ASIC design optimization methods, including LUT (Look-Up Table)-based design flow enhancements.
Company Context – Alphawave Semi:
- Alphawave Semi is a key player in high-performance semiconductor IP, focusing on silicon photonics, high-speed networking, and interconnect solutions.
- The company has demonstrated growth in the semiconductor IP market and increasing adoption of its IP blocks by leading chip manufacturers, presenting opportunities to leverage Rathish’s expertise in advanced ASIC design flows to influence future IP development and customization.
Location and Contact Information:
- Based in Bengaluru, Karnataka, India, a major technology and semiconductor hub in India, facilitating collaboration within a dense ecosystem of chip design and semiconductor engineering talent.
Notable Gaps and Observations:
- There are no publicly available records of Rathish Chandran holding patents or publishing academic papers or technical publications directly linked to him at Alphawave Semi or other prior firms.
- His profile does not indicate frequent public speaking at conferences beyond his DAC involvement, suggesting a more internally focused or leadership-driven role rather than one centered on thought leadership through publications or patents.
Summary Insight:
Rathish Chandran is a seasoned ASIC design leader with a robust foundation in physical design and timing closure. His extensive tenure in semiconductor design and leadership roles at both Intel Technology India and Alphawave Semi positions him as a critical influencer in ASIC IP development and implementation strategies within Alphawave. His involvement at international industry conferences like DAC underlines both his technical expertise and commitment to advancing ASIC design methodologies aligned with Alphawave’s cutting-edge IP offerings in high-speed data communication markets. This profile indicates a technical leader well-suited to spearhead complex ASIC design projects and collaborate on evolving semiconductor IP product offerings.
