Richard Trauben
Education
Cornell University
MSEE, Computer Architecture and VLSI Circuit Design 1981-01-01 - 1982-01-01
Rutgers University
BSEE, Electrical and Electronics Engineering 1974-01-01 - 1978-01-01Work Experience
This Gun For Hire Chip Development Consulting
Current
This Gun For Hire Chip Development Consulting
Wave Computing
2017-08-01 - 2020-01-01
Wave Computing
This Gun for Hire Chip Development Consulting
2017-05-01 - 2017-07-01
This Gun for Hire Chip Development Consulting
Huawei USA
2010-06-01 - 2017-04-01
Huawei USA
3PAR Data
2005-11-01 - 2009-09-01
3PAR Data
Mistletoe Technologies
2004-08-01 - 2005-10-01
Mistletoe Technologies
Fast-Chip
2000-04-01 - 2004-06-01
Fast-Chip
Fujitsu (HAL Computer)
1997-01-01 - 2000-03-01
Fujitsu (HAL Computer)
AMD
1995-09-01 - 1996-12-01
AMD
Sun Microsystems
1988-04-01 - 1995-08-01
Sun Microsystems
Skills
Summary
I lead the definition, development and production of VLSI components for enterprise business ecosystems that are challenging in scope and complexity. My management experience includes leading a team of 26 engineers (architects, logic, circuit, cad, physical, layout). I've helped recruit key staff members, selected architecture, design methodologies, written chip specs, selected hard macro IP and physical design tools from 3rd party vendors, partitioned designs, held feasibility studies & design reviews, established program milestones, tracked & reported progress and written employee performance reviews. My networking design experience includes developing a network security and 10Gbps router ASICs. I have architected and managed engineering teams that develop) custom packet header classification hardware. I have working knowledge of BGP, TCP/IP, Ethernet protocols & RGMII, XAUI, DDR2 and TCAM interfaces. I have managed, architected & designed processor pipelines for multiple instruction sets (VAX, SPARC, x86) with multithreaded, access-execute, out of order, superscalar execution pipelines and designed memory subsystems with cache consistency to meet memory ordering rqmts. I have 8 US patents and a working knowledge of place and route, memory circuit design, signal integrity, process, dft, packaging, software and board development. Specialties: Manager, Architect & Designer of high performance, high reliability integrated circuits. Specialized in microarchitectural definition thru timing compliant physical design methodologies for microprocessor pipelines, cache subsystems, memory controllers, switch fabrics and networking ASICS.
