Saad Z.
Education
The University of Texas at San Antonio
MS, Electrical Engineering 1996-01-01 - 1998-01-01
NED University of Engineering and Technology
Bachelor of Science, Electrical Engineering -Work Experience
Arteris
Current
Arteris
Oracle Labs
2015-08-01 - 2016-12-01
Oracle Labs
HGST, a Western Digital brand
2012-10-01 - 2015-07-01
HGST, a Western Digital brand
Huawei
2009-10-01 - 2012-10-01
Huawei
Netronome
2008-03-01 - 2009-09-01
Netronome
Tellabs
2004-06-01 - 2008-03-01
Tellabs
Axiom Design Automation
2003-02-01 - 2004-05-01
Axiom Design Automation
Conexant
1998-06-01 - 2003-01-01
Conexant
Skills
Summary
Accomplished Verification Engineer with experience in Interconnects, NoC, Caches (L1 & L2), Cache Coherency, SSD Controller, Multi-Core Network Processors and networking industries and proven track record of 7+ successful multi-million gate SoC / ASICs from concept to silicon. Excellent interpersonal and project management skills complemented by strong technical and problem solving capabilities. > Achieved functional verification closure on 9+ SoC/FPGA/ASIC by architecting and developing self-checking verification environments using System-Verilog, UVM methodologies, C++ / C, PLI, Shell & Perl Scripting. > Mastery of achieving 100% coverage by writing targeted-random, directed and corner cases on un-exercised RTL logics and boundary conditions as well as discretely random nightly regressions suites. Specialties: Interconnects verification, NoC, SystemC AT modeling, Multi-Core SoC / Caches (L1 & L2) / Cache Coherency / Performance Verification / SSD Controller / Network Processor / Traffic Manager / Test Plan / UVM / Self Checking Test bench / Constraint Random Stimulus / C & C++ Reference Model (cycle-accurate & transaction-accurate) / Scoreboard Development / Coverage Analysis / Regression / Exhaustive & Corner Cases / System-Verilog / PLI
